1. Field of the Invention
This invention generally relates to memory hardware for computer systems, and more specifically to memory expansion modules for expanding memory in computer systems.
2. Description of the Related Art
Many modem computer systems allow for memory expansion by way of single inline memory modules (SIMMs) and/or dual inline memory modules (DIMMs). SIMMs and DIMMs include small, compact circuit boards that are designed to mount easily into an expansion socket mounted on another circuit board, typically a computer motherboard. The circuit boards used to implement SIMMs and DIMMs include an edge connector comprising a plurality of contact pads, with contact pads typically being present on both sides of the circuit board. On SIMMs, opposing contact pads are connected together (i.e. shorted), and thus carry the same signal, while at least some opposing contact pads on DIMMs are not connected, thus allowing different signals to be carried. Due to this, higher signal density may be accommodated by DIMMs.
Memory elements of SIMMs and DIMMs are typically Dynamic Random Access Memory (DRAM) chips. DRAM chips store information as a charge on a capacitor, with the charge level representing a logic one or logic zero. Since a capacitor charge will dissipate over time, DRAM chips require refresh cycles on a periodic basis.
To access a location in a DRAM, an address must first be applied to the address inputs. This address is then decoded, and data from the given address is accessed. In modem DRAMs, rows and columns are addressed separately using row address strobe (RAS) and column address strobe (CAS) control signals. By using RAS and CAS signals, row and column addresses can be time-multiplexed on common signal lines, contact pads, and pins of the address bus. This allows a greater number of memory locations that can be addressed without a corresponding increase in the number of required signal lines, contact pads, and pins.
To address a memory location in a DRAM as described above, a RAS signal is asserted on the RAS input of the DRAM, and a row address is forwarded to row decode logic on a memory chip. The contents of all locations in the addressed row will then be sent to a column decoder, which is typically a combination multiplexer/demultiplexer. After row addressing is complete, a CAS signal is asserted, and a column address is sent to the column decoder. The multiplexer in the column decoder will then select the corresponding column from the addressed row, and the data from that specific row/column address is placed on the data bus for used by the computer system.
The demand for more memory in computer systems is ever increasing. Advances in software has further driven the demand for greater memory capacity, as complex programs require more memory space with which to operate. Along with the demand for greater memory capacity is the need for greater reliability in computer system operation. As the capacity of memory modules increases so to does the possibility of an error or a failure. Tracking errors to their source on a memory module may sometimes be a difficult and time-consuming process. Tracing a signal from a contact on an edge connector to a specific pin on a memory device may be time consuming even when accurate schematics are available. Furthermore, manually tracing a signal from an edge connector contact to a pin on a memory device may be prone to human error.
The problems outlined above may in large part be solved by a memory expansion module in accordance with the present invention. In one embodiment, a memory module s includes a printed circuit board with a connector edge adapted for insertion in an expansion socket of a computer system. Mounted upon the circuit board is a plurality of stacked memory packages. Each stacked memory chip package contains multiple memory chips, or die, within the package. These memory chips are typically Dynamic Random Access Memory (DRAM). In one embodiment, each stacked memory package includes two DRAM die. The printed circuit board of this embodiment includes 18 locations for mounting the stacked memory packages, resulting in a memory module with a total of 36 memory die. Also mounted upon the printed circuit board is at least one buffer (or line driver) chip for driving address and control signals to the plurality of memory die contained within the stacked memory packages. A clock driver chip is also mounted upon the printed circuit board for driving clock signals to the memory chips. Also mounted on the printed circuit board is a storage unit, which provides module identification and signal routing information. In one embodiment, a serial electrically erasable programmable read-only memory (SEEPROM) is used to implement the storage unit. Information which correlates individual contact pads of the edge connector to individual pins of the stacked memory packages may be stored in the storage unit. Using this information, an error detected by in the memory module may be quickly traced to a specific pin of a stacked memory package.
Each memory die within each stacked memory package may be individually accessed by a computer system. Since the memory die within the stacked memory packages may be accessed individually, multiple memory banks may be formed witheach die within a given package belonging to a different memory bank. In one embodiment, each memory die is a 32Mxc3x978, resulting in a stacked memory package with a capacity of 64Mxc3x978. In general, the memory module is scalable and may be implemented with various amounts of memory capacity.
Thus, in various embodiments, the memory expansion module with stacked memory packages and error correction functionality may advantageously allow greater memory capacity. The use of stacked memory packages may allow for greater memory capacity without the need for additional circuit board area. The use of stacked memory packages with no more than two memory die each may advantageously reduce power consumption and thermal output by the memory module.